The present application relates to device structures and fabrication processes for high-density integrated circuits.
In integrated circuit device structures, it is often convenient to use polysilicon to form local interconnects. This is particularly attractive in SRAM cells, where the cross-coupled inverters require at least two gate-to-drain connections: if these connections can be implemented without using metal, layout is simplified.
In CMOS devices, one of the limitations on this is that diffusion between n+ and p+ regions may cause counterdoping (where p-type and n-type dopant contributions offset each other). Counterdoping may cause increased resistance (since the effective doping will become lower), and may even cause changes in the device threshold voltage if the counterdoping affects the polysilicon doping over a transistor channel.
If polysilicon is doped n+ (as is most common), then a direct connection between polysilicon and a PMOS drain region will form a diode, which will be inherently susceptible m counterdoping effects.
One approach to this is to interpose a diffusion barrier (e.g. TiN) between e polysilicon and the p+ drain regions. However, this is not possible in all processes.
A further complication is dopant diffusion though silicides: common dopants may diffuse very rapidly in colony used silicides. Silicides are often used m strap polysilicon layers, but lateral diffusion through the silicide increases the counterdoping problems.
Many papers have proposed use of polysilicon with two doping types: n+ polysilicon provides the gates of NMOS devices, and p+ polysilicon provides the gates of PMOS devices. Junctions between n+ and p+ may be avoided (by resorting to metal jumpers to make connection), or may be shunted by metal or silicide strapping. See e.g. U.S. Pat. No. 4,985,746 to Asahina and 3,673,471 to Klein et al.
Commonly-owned prior application Ser. No. 08/069,083 (93-C-33), filed May 28 1993, which is hereby incorporated by reference, disclosed a process using polysilicon for local interconnect, wherein masked implantation of the second polysilicon layer is used to assure that p+/n+ junctions are located as lateral junctions in the second polysilicon layer rather than at the contact to PMOS source/drain regions. Silicide cladding is then applied to short out these lateral junctions. A continuation of this application is currently pending as Ser. No. 08/359,006 filed Dec. 19, 1994, and a divisional of this application is currently pending as Ser. No. 08/420,353 filed Apr. 19, 1995.
The present application provides new local interconnect structures and processes using dual-doped polysilicon. A single implant dopes part of the polysilicon local interconnect layer p-type, and also diffuses through the polysilicon interconnect layer to enhance the doping of the PMOS drain regions, and also (optionally) adds to the doping of the PMOS source regions to provide source/drain asymmetry.
The polysilicon interconnect layer is clad to reduce its conductivity, e.g. by being salicided. Optionally, the cladding which shunts the lateral polysilicon junction is patterned rather than global, so that the diode can be used as a load element if desired.